Dynamic Hot Carrier Degradation Behavior of Polycrystalline Silicon Thin-Film Transistors under Gate Voltage Pulse Stress with Fast Transition Time-Reference-Cited by-同舟云学术

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Dynamic Hot Carrier Degradation Behavior of Polycrystalline Silicon Thin-Film Transistors under Gate Voltage Pulse Stress with Fast Transition Time

Published:2023-07-24 Issue: Volume: Page:
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Container-title:2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
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Author:

Zhang Meng¹,Wang Yunyang²,Jiang Zhendong¹,Xu Xindi²,Huang Jinyang²,Wong Man³,Kwok Hoi-Sing³

Affiliation:

1. Shenzhen University,College of Electronics and Information Engineering,Shenzhen,518060

2. Shenzhen University,Institute of Microscale Optoelectronics (IMO),Shenzhen,China,518060

3. The Hong Kong University of Science and Technology,State Key Laboratory of Advanced Displays and Optoelectronics Technologies,Kowloon,Hong Kong

Funder

National Natural Science Foundation of China

Innovation and Technology Fund

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10248978/10248979/10249065.pdf?arnumber=10249065

Reference32 articles.

1. An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

2. Analysis of Poly-Si TFT Degradation Under Gate Pulse Stress Using the Slicing Model

3. Effects of the Timing of AC Stress on Device Degradation Produced by Trap States in Low-Temperature Polycrystalline-Silicon TFTs

4. Degradation of metal-induced laterally crystallized n-type poly-Si thin-film transistors under dynamic voltage stress

5. Optimized Design of Carrier Injection Terminal for Reliable Low-Temperature Poly-Si TFTs Under Dynamic Hot-Carrier Stress

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