SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks-Reference-Cited by-同舟云学术

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SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks

Published:2024-04-17 Issue: Volume: Page:1-6
ISSN:
Container-title:2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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Author:

Kojima Takuya¹,Yanai Yosuke²,Okuhara Hayate³,Amano Hideharu²,Kuga Morihiro⁴,Iida Masahiro⁴

Affiliation:

1. The University of Tokyo,Graduate School of Information Science and Technology,Tokyo,Japan

2. Keio University,Department of Information and Computer Science,Yokohama,Japan

3. National University of Singapore,Department of Electrical and Computer Engineering,Singapore

4. Kumamoto University,Department of Computer Science and Electrical Engineering,Kumamoto,Japan

Funder

Cadence Design Systems

Synopsys

Mentor Graphics

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10531139/10531159/10531161.pdf?arnumber=10531161

Reference13 articles.

1. Are FPGAs Suitable for Edge Computing?;Biookaghazadeh

2. Zynq 7000 data sheet:overview

3. An eFPGA Generation Suite with Customizable Architecture and IDE

4. CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm² 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

5. Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes

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