An eFPGA Generation Suite with Customizable Architecture and IDE

Author:

KUGA Morihiro1,ZHAO Qian2,NAKAZATO Yuya3,AMAGASAKI Motoki1,IIDA Masahiro1

Affiliation:

1. Faculty of Advanced Science and Thechnology, Kumamoto University

2. Kyushu Institute of Technology

3. Dept. of Graduate School of Science and Thechnology, Kumamoto University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference32 articles.

1. [1] Xilinx, Zynq-7000 SoC Overview, 2018. Retrieved Oct. 14, 2021 from https://www.xilinx.com/content/dam/xilinx/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf

2. [2] Achronix, Speedcore eFPGA Product Brief (PB028), 2020. Retrieved Oct. 14, 2021 from https://www.achronix.com/sites/default/files/docs/Speedcore_eFPGA_Product_Brief_PB028.pdf

3. [3] QuickLogic, ArcticPro eFPGA, 2021. Retrieved Oct. 14, 2021 from https://www.quicklogic.com/products/efpga/arcticpro-2/

4. [4] FlexLogix, EFLX® eFPGA, 2021. Retrieved Oct. 14, 2021 from https://flex-logix.com/efpga/

5. [5] P. Mohan, O. Atli, O. Kibar, M. Zackriya, L. Pileggi, and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” Proc. ACM/SIGDA Int'l Symp. on Field Programmable Gate Arrays (FPGA'21), pp.1-10, 2021. https://doi.org/10.1145/3431920.3439297 10.1145/3431920.3439297

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1. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks;2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2024-04-17

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