Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C-Reference-Cited by-同舟云学术

Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Published:2022-12-03 Issue: Volume: Page:
ISSN:
Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Tsui Bing-Yue¹,Tsai Te-Kai¹,Hung Chia-Lung¹,Wen Yu-Xin¹

Affiliation:

1. National Yang Ming Chiao Tung University,Institute of Electronics,Hsinchu,Taiwan, R.O.C.

Funder

Ministry of Science and Technology

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019434.pdf?arnumber=10019434

Reference6 articles.

1. Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

2. A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process

3. First Integration of 10-V CMOS Logic Circuit, 20-V Gate Driver, and 600-V VDMOSFET on a 4H-SiC Single Chip

4. First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer

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