A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

Abstract

Process Variation (PV), Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB) are the critical factors that affect the reliability of semiconductor chip design. They cause the system to be unstable and increase the soft error rate. In this paper, a compact on-chip degradation technique using runtime leakage current monitoring has been proposed. The proposed sensor-based adaptive technique compensates for the variation due to PV and aging using the body-bias-voltage-generator circuit. Simulation experiments for three and ten-year stress have been performed. Simulation results proved the superiority of the proposed sensor which provides 33% (up to 0.75 V) more output voltage and 98% sensitivity at 1 V supply voltage compared to the state-of-the-art sensor. The proposed technique mitigates up to 80% PV and BTI effects in SRAM compared to the state-of-the-art techniques.