From Chip to Cooling Tower Data Center Modeling: Chip Leakage Power and Its Impact on Cooling Infrastructure Energy Efficiency
Author:
Affiliation:
1. e-mail:
2. Stokes Institute, University of Limerick, Limerick, Ireland
3. Hewlett-Packard Laboratories, Palo Alto, CA 94304
4. HP Enterprise Business, Liberty Lake, WA 99019
Abstract
Publisher
ASME International
Subject
Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials
Link
http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/doi/10.1115/1.4007744/6138436/ep_134_4_041009.pdf
Reference18 articles.
1. Scaramella, J., 2008, “Next-Generation Power and Cooling for Blade Environments,” IDC Technical Report No. 215675.
2. Estimating Total Power Consumption by Servers in the U.S. and the World,2007
3. Shah, A., Patel, C., Bash, C., Sharma, R., and Shih, R., 2008, “Impact of Rack-Level Compaction on the Data Center Cooling Ensemble,” Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Orlando, FL, May 28–31.
4. From Chip to Cooling Tower Data Center Modeling: Influence of Server Inlet Temperature and Temperature Rise Across Cabinet;ASME J. Electron. Packag.,2011
5. From Chip to Cooling Tower Data Center Modeling: Influence of Chip Temperature Control Philosophy;ASME J. Electron. Packag.,2011
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