A Novel Design of High Performance Two-Stage Operational Amplifier using CMOS Technology
Author:
Affiliation:
1. VNR VJIET, Bachupally,Department of ECE,India,500090
2. VNR VJIET, Bachupally,Department of ECE,Hyderabad,India,500090
3. NIT Warangal,Department of ECE,India,560064
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10498131/10498150/10498993.pdf?arnumber=10498993
Reference30 articles.
1. Design procedure for two-stage CMOS operational amplifiers employing current buffer
2. Design and comparative analysis of a two-stage ultra-low-power subthreshold operational amplifier in 180nm, 90nm, and 45nm technology;Singh
3. Design and Implementation of 1KB SRAM array in 45 nm Technology for Low-Power Applications
4. A high speed two stage operational amplifier with high CMRR;Bhadra
5. Design of two stage operational amplifier and implementation of flash ADC;Samson
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