Author:
Castellana Vito Giovanni,Tumeo Antonino,Ferrandi Fabrizio
Cited by
6 articles.
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1. SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27
2. Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets;IEEE Transactions on Computers;2023-11-01
3. Parallelising Control Flow in Dynamic-scheduling High-level Synthesis;ACM Transactions on Reconfigurable Technology and Systems;2023-09
4. Efficient Memory Arbitration in High-Level Synthesis from Multi-threaded Code;IEEE Transactions on Computers;2021
5. Combining Dynamic & Static Scheduling in High-level Synthesis;Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2020-02-23