SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference
Author:
Affiliation:
1. School of Electronic Science and Engineering, Nanjing University, Nanjing, China
2. Beijing Zhicun (Witmem) Technology Company Ltd., Beijing, China
Funder
National Key Research and Development Program of China
National NSF of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10296081/10214415.pdf?arnumber=10214415
Reference47 articles.
1. 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing
2. A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference
3. An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices
4. A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks
5. In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array
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1. A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07
3. Reconfigurable Precision SRAM-based Analog In-memory-compute Macro Design;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
4. BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
5. An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024
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