Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

Author:

Lei Seong-I,Mak Wai-Kei

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Evaluating Results of PCB Routing Based on the Two-Dimensional Entropy Model;2024 13th International Conference on Communications, Circuits and Systems (ICCCAS);2024-05-10

2. Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-03

3. URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-01

4. Pin Assignment Optimization for Multi-2.5D FPGA-based Systems;Proceedings of the 2018 International Symposium on Physical Design;2018-03-25

5. Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-02

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