A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression-Reference-Cited by-同舟云学术

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A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression

Published:2024-08 Issue:8 Volume:71 Page:3940-3944
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Cheshmikhani Elham¹^ORCID,Shokouhinia Fateme²^ORCID,Farbeh Hamed³^ORCID

Affiliation:

1. Department of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran

2. Department of Computing Science, Simon Fraser University, Burnaby, BC, Canada

3. Department of Computer Engineering, Amirkabir University of Technology, Tehran, Iran

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10617442/10466368.pdf?arnumber=10466368

Reference32 articles.

1. BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture

2. Domain Wall Tilting in the Presence of the Dzyaloshinskii-Moriya Interaction in Out-of-Plane Magnetized Magnetic Nanotracks

3. DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories

4. Multilane Racetrack caches: Improving efficiency through compression and independent shifting

5. A Novel Transverse Read Technique for Domain-Wall “Racetrack” Memories

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