Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology
Author:
Affiliation:
1. University of Pavia,Microelectronics Lab,Pavia,Italy
2. Marvell,Pavia,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10161731/10161695/10161758.pdf?arnumber=10161758
Reference8 articles.
1. The Factors that Inflence the Effective Mobility in 5 NM PMOS Finfet Design
2. Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier
3. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise
4. A 174?VRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch;bindra;IEEE Int Solid-State Circuit Conf (ISSCC),2022
5. A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
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