BEOL-Compatible MFMIS Ferroelectric/ Anti-ferroelectric FETs—Part II: Mechanism With Load Line Analysis and Scaling Strategy-Reference-Cited by-同舟云学术

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BEOL-Compatible MFMIS Ferroelectric/ Anti-ferroelectric FETs—Part II: Mechanism With Load Line Analysis and Scaling Strategy

Published:2024-09 Issue:9 Volume:71 Page:5325-5331
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Zheng Zijie¹^ORCID,Zhang Dong¹^ORCID,Jiao Leming¹^ORCID,Sun Chen¹^ORCID,Zhou Zuopu¹^ORCID,Chen Yue¹,Kong Qiwen¹^ORCID,Wang Xiaolin¹^ORCID,Liu Gan¹^ORCID,Ni Kai²^ORCID,Gong Xiao¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, National University of Singapore, Queenstown, Singapore

2. Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA

Funder

Singapore Ministry of Education

Advanced Research and Technology Innovation Centre (ARTIC), Singapore Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/16/10645717/10609350.pdf?arnumber=10609350

Reference29 articles.

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4. Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

5. Hybrid FeRAM/RRAM Synaptic Circuit Enabling On-Chip Inference and Learning at the Edge

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