A Geometrical Optimization Rule of the Synaptic Pass-Transistor for a Low Power Analog Accelerator-Reference-Cited by-同舟云学术

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A Geometrical Optimization Rule of the Synaptic Pass-Transistor for a Low Power Analog Accelerator

Published:2022 Issue: Volume:10 Page:35120-35130
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Cha Danyoung¹^ORCID,Kang Yeonsu¹^ORCID,Lee Soobin¹,Lee Sungsik¹^ORCID

Affiliation:

1. Department of Electronics Engineering, Pusan National University, Pusan, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09743929.pdf?arnumber=9743929

Reference36 articles.

1. Towards the first adversarially robust neural network model on MNIST;schott;arXiv 1805 09190,2018

2. A Signal Processing Approach for Cyber Data Classification with Deep Neural Networks

3. A comparison study on the different SNR levels to the accuracy of two deep learning techniques in fault diagnosis of planetary gearbox

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Bias‐Dependent Weight Update Characteristics of Low Power Synaptic Pass‐Transistors with a Hf‐Doped ZnO Channel Layer;Advanced Electronic Materials;2024-06-04

2. Operating region-dependent characteristics of weight updates in synaptic In–Ga–Zn–O thin-film transistors;Scientific Reports;2022-12-12

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