Enhancing High-Speed Data Communications: Optimization of Route Controlling Network on Chip Implementation-Reference-Cited by-同舟云学术

Enhancing High-Speed Data Communications: Optimization of Route Controlling Network on Chip Implementation

Published:2024 Issue: Volume:12 Page:123514-123528
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Anuradha P.¹,Majumder Pratham²,Sivaraman Kanithan³,Vignesh N. Arun⁴^ORCID,Jayakar S. Arun⁵,Selvaraj Anthoniraj³,Mallik Saurav⁶^ORCID,Al-Rasheed Amal⁷^ORCID,Abbas Mohamed⁸,Soufiene Ben Othman⁹^ORCID

Affiliation:

1. Chaitanya Bharathi Institute of Technology, Hyderabad, Telangana, India

2. Department of ISE, JAIN (Deemed-to-be-University), Kanakapura, India

3. Department of CSE, JAIN (Deemed-to-be-University), Bengaluru, India

4. Department of ECE, GRIET, Hyderabad, India

5. Department of Electronics and Instrumentation Engineering, Bannari Amman Institute of Technology, Sathyamangalam, India

6. Department of Environmental Health, Harvard T. H. Chan School of Public Health, Boston, MA, USA

7. Department of Information Systems, College of Computer and Information Sciences, Princess Nourah Bint Abdulrahman University, P. O. Box 84428, Riyadh, Saudi Arabia

8. Electrical Engineering Department, College of Engineering, King Khalid University, Abha, Saudi Arabia

9. Prince Laboratory Research, ISITcom, Hammam Sousse, University of Sousse, Sousse, Tunisia

Funder

Princess Nourah Bint Abdulrahman University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/6287639/10380310/10597576.pdf?arnumber=10597576

Reference33 articles.

1. Sustainable Operations in IoT by Combining Spatiotemporal Data Correlation With Silent Symbol Based Communication Strategy

2. An efficient and cost effective application mapping for network-on-chip using Andean condor algorithm

3. Design alternatives of Network- on-Chip (NoC) Router microarchitecture for future Communication System

4. Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip

5. NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA