A Dual-Signaling Architecture for Enhancing Noise Resilience in Floquet Engineering-Based Chip-Scale Wireless Communication-Reference-Cited by-同舟云学术

A Dual-Signaling Architecture for Enhancing Noise Resilience in Floquet Engineering-Based Chip-Scale Wireless Communication

Published:2024-08 Issue:8 Volume:42 Page:2039-2053
ISSN:0733-8716
Container-title:IEEE Journal on Selected Areas in Communications
language:
Short-container-title:IEEE J. Select. Areas Commun.

Author:

Herath Kosala¹^ORCID,Nirmalathas Ampalavanapillai²^ORCID,Gunapala Sarath D.³^ORCID,Premaratne Malin¹^ORCID

Affiliation:

1. Department of Electrical and Computer Systems Engineering, Advanced Computing and Simulation Laboratory (AχL), Monash University, Clayton, VIC, Australia

2. Department of Electrical and Electronic Engineering, The University of Melbourne, Melbourne, VIC, Australia

3. Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA, USA

Funder

Australian Government through the Australian Research Council’s Discovery Projects

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/49/10601497/10529964.pdf?arnumber=10529964

Reference104 articles.

1. Terahertz topological photonics for on-chip communication

2. THz interconnect: the last centimeter communication

3. A Fully Integrated Broadband Sub-mmWave Chip-to-Chip Interconnect

4. Ortho-Mode Sub-THz Interconnect Channel for Planar Chip-to-Chip Communications

5. Emerging Terahertz Integrated Systems in Silicon

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