A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros-Reference-Cited by-同舟云学术

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A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
language:
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Author:

Jiang Hao¹,Zheng Jiapei¹,Wang Yunzhengmao¹,Zhang Jinshan¹,Zhu Haozhe¹,Lyu Liangjian²,Chen Yingping¹,Chen Chixiao¹,Liu Qi¹

Affiliation:

1. Frontier Institute of Chip and System, Fudan University,State Key Lab of Integrated Chips and Systems

2. School of Communication and Electronic Engineering, East China Normal University

Funder

National Natural Science Foundation of China

Chinese Academy of Sciences

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181615.pdf?arnumber=10181615

Reference12 articles.

1. Comb-mcm: Computing-on-memory-boundary nn processor with bipolar bitwise sparsity optimization for scalable multi-chiplet-module edge machine learning;zhu;IEEE International Solid-State Circuits Conference ISSCC 2022,2022

2. A 10.8 µW Neural Signal Recorder and Processor With Unsupervised Analog Classifier for Spike Sorting

3. A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering

4. An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~\mu$ W/Channel in 65-nm CMOS

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