Double Dielectric Spacer for the Enhancement of Silicon p-Channel Tunnel Field Effect Transistor Performance
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Reference9 articles.
1. P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths
2. Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source
3. Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis
4. Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates
5. Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices
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1. Impact of Process Variation on Leakage and Drive Currents of FED Structures Using Linear Regression and Random Forest Algorithms;Silicon;2023-10-25
2. Enhancing Frequency Performance of Underlap Tunnel Field-Effect Transistor for Analog/RF Applications;Journal of Nanoelectronics and Optoelectronics;2019-05-01
3. Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective;IEEE Transactions on Electron Devices;2017-07
4. Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor;Superlattices and Microstructures;2015-06
5. Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs;Japanese Journal of Applied Physics;2015-02-25
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