Ambipolarity Suppression of a Double Gate Tunnel FET using High-k Drain Dielectric Pocket

Abstract

The paper investigates the impact of placing a high-k dielectric pocket (DP) region in the drain of a double gate silicon TFET. The sheer existence of the high-k DP reduces the ambipolarity significantly due to the higher effective tunneling width at the channel/drain interface. The electrical performance investigation has been carried out by positioning the DP asymmetrically (Top or Bottom) and symmetrically on both sides of the drain. The Asymmetric DPTop configuration with an optimized thickness of 8 nm and length of 25 nm offers the lowest ambipolar current (Iamb) of 4.30 × 10−16 A μm−1 at gate voltage = −1.5 V, which is ∼7-decades lower compared to the conventional DGTFET. This reduced Iamb further provides the highest Ion/Iamb current ratio of 4.63 × 1011 without degrading the average subthreshold swing (SS) of 26 mV decade−1. The small-signal parameter study and RF performance analysis of the device structure have also been carried out. The proposed TFET configuration can be one of the potential devices to be used in ultra-low-power integrated circuits and SRAM digital circuits owing to its suppressed ambipolarity and ease in the fabrication process.