Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model-Reference-Cited by-同舟云学术

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Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model

Published:2024-08-02 Issue:1 Volume:14 Page:
ISSN:2045-2322
Container-title:Scientific Reports
language:en
Short-container-title:Sci Rep

Author:

Lim Jae Gwang,Park Sung-jae,Lee Sang Min,Jeong Yeonjoo,Kim Jaewook,Lee Suyoun,Park Jongkil,Hwang Gyu Weon,Lee Kyeong-Seok,Park Seongsik,Jang Hyun Jae,Ju Byeong-Kwon,Park Jong Keuk,Kim Inho

Funder

Korea Institute of Science and Technology

Publisher

Springer Science and Business Media LLC

Link

https://www.nature.com/articles/s41598-024-68359-x.pdf

Reference58 articles.

1. Beyond von Neumann. Nat. Nanotechnol. 15, 507. https://doi.org/10.1038/s41565-020-0738-x (2020).

2. Davies, M. et al. Loihi: A neuromorphic manycore processor with on-chip learning. IEEE Micro 38, 82–99. https://doi.org/10.1109/mm.2018.112130359 (2018).

3. Orchard, G. et al. In 2021 IEEE Workshop on Signal Processing Systems (SiPS) 254–259 (2021).

4. Akopyan, F. et al. TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 34, 1537–1557. https://doi.org/10.1109/tcad.2015.2474396 (2015).

5. Deng, L. et al. Tianjic: A unified and scalable chip bridging spike-based and continuous neural computation. IEEE J. Solid-State Circuits 55, 2228–2246. https://doi.org/10.1109/jssc.2020.2970709 (2020).

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