Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD-Reference-Cited by-同舟云学术

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Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

Published:2024-06-05 Issue:24 Volume:16 Page:31624-31635
ISSN:1944-8244
Container-title:ACS Applied Materials & Interfaces
language:en
Short-container-title:ACS Appl. Mater. Interfaces

Author:

Jousseaume Vincent¹^ORCID,Guerin Chloe¹,Ichiki Kazuya²,Lagrange Mélanie¹,Altemus Bruce²,Zavvou Chara¹,Veillerot Marc¹,Mourier Thierry¹,Faguet Jacques³

Affiliation:

1. Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble, France

2. US-Technology Development Center, TEL Technology Center, America, LLC, 255 Fuller Road, Suite 214, Albany, New York 12203, United States

3. US-Technology Development Center, TEL Technology Center, America, LLC, 2400 Grove Boulevard, Austin, Texas 78741, United States

Funder

IRT 3D Nanoelec program

Publisher

American Chemical Society (ACS)

Link

https://pubs.acs.org/doi/pdf/10.1021/acsami.4c05683

Reference67 articles.

1. High-Density Through Silicon Vias for 3-D LSIs

2. Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

3. Three-dimensional silicon integration

4. Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

5. Reliability challenges of through-silicon-via (TSV) stacked memory chips for 3-D integration: From transistors to packages

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