Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates-Reference-Cited by-同舟云学术

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates

Published:2016-07-12 Issue:29 Volume:8 Page:19110-19118
ISSN:1944-8244
Container-title:ACS Applied Materials & Interfaces
language:en
Short-container-title:ACS Appl. Mater. Interfaces

Author:

Zhang Liangliang¹,Guo Yuzheng²,Hassan Vinayak Vishwanath³,Tang Kechao⁴,Foad Majeed A.³,Woicik Joseph C.⁵,Pianetta Piero⁶,Robertson John²,McIntyre Paul C.⁴

Affiliation:

1. Department of Electrical Engineering, Stanford University, Stanford, California 94305, United States

2. Engineering Department, Cambridge University, Cambridge CB2 1PZ, United Kingdom

3. Applied Materials, Santa Clara, California 95054, United States

4. Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, United States

5. Materials Science and Engineering Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899, United States

6. SLAC National Accelerator Center, Menlo Park, California 94025, United States

Publisher

American Chemical Society (ACS)

Subject

General Materials Science

Link

https://pubs.acs.org/doi/pdf/10.1021/acsami.6b03331

Reference35 articles.

1. (Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling

2. Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

3. First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications

4. Effects of Si passivation on Ge metal-insulator-semiconductor interface properties and inversion-layer hole mobility

5. Structural and electrical characterization of Al2O3/HfO2/Al2O3 on strained SiGe

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