Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure
-
Published:2021-06-28
Issue:13
Volume:10
Page:1561
-
ISSN:2079-9292
-
Container-title:Electronics
-
language:en
-
Short-container-title:Electronics
Author:
Choi Seonjun1, Choi Changhwan2, Jeong Jae Kyeong1ORCID, Kang Myounggon3ORCID, Song Yun-heub1
Affiliation:
1. Department of Electronics Engineering, Hanyang University, Seoul 04763, Korea 2. Division of Material Science and Engineering, Hanyang University, Seoul 04763, Korea 3. Department of Electronics Engineering, Korea National University of Transportation, Chung-ju 27469, Korea
Abstract
In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV.
Funder
Ministry of Trade, Industry & Energy grant from Samsung Research Funding & Incubation Center 352 of Samsung Electronics
Reference20 articles.
1. Tanaka, H., Kido, M., Yahashi, K., Oomura, M., Katsumata, R., Kito, M., Fukuzumi, Y., Sato, M., Nagata, Y., and Matsuoka, Y. (2007). Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory. Symp. VLSI Tech., 14–15. 2. Jang, J., Kim, H.S., Cho, W., Cho, H., Kim, J., Shim, S.L., Jang, Y., Jeong, J.H., Son, B.K., and Kim, D.W. (2009, January 15–17). Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for UltraHigh Density NAND Flash Memory. Proceedings of the 2009 Symposium on VLSI Technology, Kyoto, Japan. 3. Choi, E.S., and Park, S.K. (2012). Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in Near Future. IEDM Tech. Dig., 211–214. 4. (2021, June 24). NAND Flash Memory Technology/Products Roadmap. Available online: http://www.techinsights.com. 5. A drain leakage phenomenon in poly silicon channel 3D NAND flash caused by conductive paths along grain boundaries;Wang;Microelectron. Eng.,2018
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|