High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs

Abstract

To avoid soft errors in integrated circuits, this paper presents two high-performance latch designs, namely LOCDNUTRL and LOCTNUTRL, protecting against double-node upset (DNU) and triple-node upset (TNU) in the harsh radiation environment. First, the LOCDNUTRL latch consists of two single-node upset (SNU) self-recovery modules and uses a C-element at the output. Next, based on the LOCDNUTRL latch, the LOCTNUTRL latch is proposed, which uses five extra inverters to fully tolerate TNU. Unlike the LOCDNUTRL latch, which uses an output level C-element as a voter, LOCTNUTRL is insensitive to the high-impedance state (HIS), making it more reliable for aerospace applications. The HSPICE simulation results, using a predictive technology model, show that the LOCTNUTRL latch saves 57.74% delay, 7.7% power consumption, 11.74% area cost, and 63.59% power delay production (PDP) on average compared with the state-of-the-art hardened latches. The process, voltage, and temperature variation analysis show that the proposed two latches are less sensitive to changes.