Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors

Author:

Lauritano Mario12ORCID,Baumgartner Peter1ORCID,Çağri Ulusoy Ahmet2

Affiliation:

1. Intel Germany, 85579 Neubiberg, Germany

2. Institute of Radio Frequency Engineering and Electronics (IHE), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, Germany

Abstract

The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16 nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios.

Funder

Intel Deutschland GmbH

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

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