FPIA: Field-Programmable Ising Arrays with In-Memory Computing-Reference-Cited by-同舟云学术

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FPIA: Field-Programmable Ising Arrays with In-Memory Computing

Published:2024-08-05 Issue: Volume:6 Page:1-6
ISSN:
Container-title:Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design
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Short-container-title:

Author:

Hutchinson George Higgins¹^ORCID,Sifferman Ethan²^ORCID,Bhattacharya Tinish²^ORCID,Kwon Dongseok²^ORCID,Strukov Dmitri B²^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, United States

2. Department of Electrical and Computer Engineering, UC Santa Barbara, Santa Barbara, CA, United States

Funder

Defense Advanced Research Projects Agency

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3665314.3670851

Reference36 articles.

1. S. Agarwal S.J. Plimpton D.R. Hughart et al. 2016. Resistive memory device requirements for a neural algorithm accelerator. In IJCNN. 929--938.

2. T. Balyo, N. Froleyks, M.J.H. Heule, et al. 2020. Proceedings of SAT Competition 2020 : Solver and Benchmark Descriptions. http://hdl.handle.net/10138/318450

3. T. Balyo, M.J.H. Heule, and M. Järvisalo. 2017. Proceedings of SAT Competition 2017 : Solver and Benchmark Descriptions. http://hdl.handle.net/10138/224324

4. aCortex: An Energy-Efficient Multipurpose Mixed-Signal Inference Accelerator;Bavandpour M.;IEEE JXCDC,2020

5. V. Betz and J. Rose. 1997. VPR: a new packing, placement and routing tool for FPGA research. Lecture Notes in Computer Science, Vol. 1304. Springer Berlin Heidelberg, Berlin, Heidelberg, 213--222.

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