AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG

Author:

Shi Yichen1ORCID,TAO ZHUOFU2ORCID,Gao YuHao3ORCID,Zhou Tianjia4ORCID,Chang Cheng4ORCID,Wang Yaxin5ORCID,Chen Bingyu4ORCID,Zhang Genhao4ORCID,Liu Alvin3ORCID,Yu Zhiping6ORCID,Lin Ting-Jung789ORCID,He Lei2ORCID

Affiliation:

1. Eastern Institute of Technology, Ningbo, China

2. Electrical Engineering, University of California Los Angeles, Los Angeles, United States

3. BTD Tech Inc., Ningbo China

4. University of California Los Angeles, Los Angeles, United States

5. Electronic and Information College, University of California Los Angeles, Los Angeles, United States

6. Tsinghua University, Beijing, China

7. Chiplet CAD and Manufacturing Research Center of Zhejiang Province, Ningbo China

8. Ningbo Institute of Digital Twin, Ningbo China

9. Eastern Institute of Technology, Ningbo China

Abstract

High-performance analog and mixed-signal (AMS) circuits are mainly full-custom designed, which is time-consuming and labor-intensive. A significant portion of the effort is experience-driven, which makes the automation of AMS circuit design a formidable challenge. Large language models (LLMs) have emerged as powerful tools for Electronic Design Automation (EDA) applications, fostering advancements in the automatic design process for large-scale AMS circuits. However, the absence of high-quality datasets has led to issues such as model hallucination, which undermines the robustness of automatically generated circuit designs. To address this issue, this paper introduces AMSnet-KG, a dataset encompassing various AMS circuit schematics and netlists. We construct a knowledge graph with annotations on detailed functional and performance characteristics. Facilitated by AMSnet-KG, we propose an automated AMS circuit generation framework that utilizes the comprehensive knowledge embedded in LLMs. The flow first formulate a design strategy (e.g., circuit architecture using a number of circuit components) based on required specifications. Next, matched subcircuits are retrieved and assembled into a complete topology, and transistor sizing is obtained through Bayesian optimization. Simulation results of the netlist are automatically fed back to the LLM for further topology refinement, ensuring the circuit design specifications are met. We perform case studies of operational amplifier and comparator design to verify the automatic design flow from specifications to netlists with minimal human effort. The dataset used in this paper is available at https://ams-net.github.io/.

Publisher

Association for Computing Machinery (ACM)

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5. Yao Lu, Shang Liu, Qijun Zhang, and Zhiyao Xie. 2024. RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 722–727.

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