1. (1) K. Ueda, K. Takasugi, T. Yamanaka, and K. Sasaki : “A 16Mb SRAM with A Single-Bit-Line Memory Cell”, Technical Report of IEICE, Vol. 93, No. 111, pp. 9-16 (1993) (in Japanese)
2. (2) T. Mori, S. Nakamura, T. Inata, S. Muto, H. Tamura, and N. Yokoyama : “A SRAM Cell A Double-Emitter Resonant-tunneling Hot Electron Transistor Structure”, Technical Report of IEICE, Vol. 93, No. 12, pp. 55-62 (1993) (in Japanese)
3. (3) T. Kimura and T. Oguri : “A New, 0.8V Logic Swing, 1.6V Operative High Speed BiCMOS Circuit”, Technical Report of IEICE, Vol. 93, No. 111, pp. 9-16 (1993) (in Japanese)
4. (4) L. Esaki : “New phenomenon in Narrow Germanium p-n Junctions”, Phys. Rev., Vol. 109, No. 2, pp. 603-604 (1958)
5. (5) L. L. Chang, L. Esaki, and R. Tsu : “Resonant tunneling in semiconductor double barriers”, Appl. Phys. Lett., Vol. 24, No. 12, pp. 593-595 (1974)