A strategy for damage assessment of thermally stressed copper vias in microelectronic printed circuit boards-Reference-Cited by-同舟云学术

A strategy for damage assessment of thermally stressed copper vias in microelectronic printed circuit boards

Published:2008-01 Issue:1 Volume:48 Page:68-82
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Weinberg K.,Müller W.H.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. Albrecht HJ, Jendry J, Müller WH, Wieand C. Lebensdauervorhersagen für Vias und Mikrovias in HDI-Boards per FE-Simulation und ihre experimentelle Verifikation. In: Wolter KJ, Wiese S, editors. Interdisziplinäre Methoden in der Aufbau-und Verbindungstechnik. ddp goldenbogen: Dresden; 2003.

2. Albrecht HJ, Jendry J, Müller WH, Wieand C. Lifetime prediction by fe-simulation and experimental verification for vias and microvias in HDI-substrates. In: Proc. of eighth Ann. Pan Pacific microelectronic symposium (SMTA), Hawai; 2003. p. 201–8.

3. Thermal analysis in plated-through-hole reliability;Barker,1993

4. Dubbel-Taschenbuch für den Maschinenbau;Beitz,1990

5. DiTomasso JC. Stress analysis of vias within general electric’s multichip modules. University of Massachusetts at Amherst, MA, report provided on the web, http://www.ecs.umass.edu/mie/labs/mda/fea/ditomaso/Main.htm; 2000.

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