Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors-Reference-Cited by-同舟云学术

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Published:2024-01 Issue: Volume:211 Page:108805
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Wang Y.^ORCID,Mukherjee C.,Rezgui H.,Deng M.^ORCID,Müller J.,Pelloquin S.^ORCID,Larrieu G.,Maneux C.

Funder

Horizon 2020

Horizon 2020 Framework Programme

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference16 articles.

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5. C. Mukherjee, C. Maneux, J. Pezard and G. Larrieu, “1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors,” 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, 2017, pp. 34-37.

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1. 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2023-12