CMOS downsizing toward sub-10 nm-Reference-Cited by-同舟云学术

CMOS downsizing toward sub-10 nm

Published:2004-04 Issue:4 Volume:48 Page:497-503
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Iwai Hiroshi

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference6 articles.

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2. Doris B et al. Extreme scaling with ultra-thin SOI channel MOSFETs. In: IEDM Tech Dig, December 2002, San Francisco. p. 267–70

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4. Introduction to VLSI systems;Mead,1979

5. Gelsinger PP. Microprocessor for the new millenium: challenges, opportunities, and new frontiers. In: Dig. Tech. 2001 IEEE International Solid-State Circuits Conference, February 2001, San Francisco. p. 22–3

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