Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below-Reference-Cited by-同舟云学术

Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

Published:2010-09 Issue:9 Volume:54 Page:849-854
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Fenouillet-Beranger C.,Perreau P.,Denorme S.,Tosti L.,Andrieu F.,Weber O.,Monfray S.,Barnola S.,Arvet C.,Campidelli Y.,Haendler S.,Beneyton R.,Perrot C.,de Buttet C.,Gros P.,Pham-Nguyen L.,Leverd F.,Gouraud P.,Abbate F.,Baron F.,Torres A.,Laviron C.,Pinzelli L.,Vetier J.,Borowiak C.,Margain A.,Delprat D.,Boedt F.,Bourdelle K.,Nguyen B.-Y.,Faynot O.,Skotnicki T.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Fenouillet-Beranger C et al. Fully-depleted SOI technology using high-k and single metal gate for 32nm node LSTP applications featuring 0.179μm2 6T-SRAM bitcell. In: IEDM technical digest; 2007. p. 267–70.

2. Weber O et al. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding. In: IEDM technical digest; 2008. p. 245–8.

3. Sugii N et al. Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation. In: IEDM technical digest; 2008. p. 249–52.

4. Fenouillet-Beranger C et al. FDSOI devices with thin BOX and ground plane integration for 32nm node and below. In: IEEE ESSDERC; 2008. p. 206–09.

5. Noel J-P et al. A simple and efficient concept for setting up multi-VT devices in thin BOX fully-depleted SOI technology. In: IEEE ESSDERC; 2009. p. 137–40.

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