An improved wide-range, low-complexity, fully-parallel digital background timing mismatch calibration method for dual-channel TIADC based on perfect reconstruction filter bank

Author:

Liu Yu,Zhang Zhenwei,Xiong Wei,Sun LinORCID,Lang Lili,Wu Xufan,Dong YeminORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference31 articles.

1. Time interleaved converter arrays;Black;IEEE J Solid State Circuits,1980

2. A 10-Bit 600-MS/s Time-Interleaved SAR ADC with interpolation-based timing skew calibration;Li;IEEE Trans Circuits Syst,2019

3. Fully digital background calibration of channel mismatches in time-interleaved ADCs using recursive least square algorithm;Hoang;AEU-Int J Electron C,2021

4. Joint background calibration of gain and timing mismatch errors with low hardware cost for time-interleaved ADCs;Zhang;IET Circuits Devices Syst,2019

5. Background analog and mixed signal calibration system for time-interleaved ADC;Khalil;Microelectron J,2015

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