Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance-Reference-Cited by-同舟云学术

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Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance

Published:2024-09 Issue: Volume:151 Page:106309
ISSN:1879-2391
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Anam Aadil,Amin S. Intekhab^ORCID,Prasad Dinesh

Publisher

Elsevier BV

Reference85 articles.

1. Double gate strained-Ge heterostructure tunneling FET (TFET) with record high drive current and <60 mV/dec subthreshold slope;Krishnamohan;IEDM Tech. Dig.,2008

2. Impact of SOI, Si1−xGexOI and GeOI substrates on CMOS compatible tunnel FET performance;Mayer;IEDM Tech. Dig.,2008

3. Modeling of high-performance p-type III–V heterojunction tunnel FETs;Knoch;IEEE Electron. Device Lett.,2010

4. 1D broken-gap tunnel transistor with MOSFET-like on-currents and sub-60 mV/dec subthreshold swing;Koswatta;IEDM Tech. Dig.,2009

5. Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source;Xie;Semicond. Sci. Technol.,2020

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