Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors

Author:

Li Qingkun,Cao Lei,Zhang Qingzhu,Li Lianlian,Zhang Xuexiang,Niu Chuqiao,Sang Guanqiao,Bao Yunjiao,Yin HuaxiangORCID,Wu ZhenhuaORCID

Funder

Chinese Academy of Sciences

Publisher

Elsevier BV

Reference23 articles.

1. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates;Mertens,2016

2. 5-nm gate-all-around transistor technology with 3-D stacked nanosheets;Gundu;IEEE Trans. Electron. Dev.,2022

3. “(Invited) evaluation of stacked nanowires transistors for CMOS: performance and technology opportunities,”;Gaben;ECS Trans.,2016

4. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET;Loubet,2017

5. Physical insights on quantum confinement and carrier mobility in Si, Si0.45Ge0.55, Ge gate-all-around NSFET for 5nm technology node;Yao;IEEE J. Electron Devices Soc.,2018

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