1. Design and analysis of analog performance of dual-k spacer Underlap N/P-FinFET at 12 nm gate length;Nandi;IEEE Trans. Electron. Dev.,2013
2. FPGA implementation of a low power, processor-independent and reusable System-on-Chip platform;ul Haq,2009
3. The role of geometry parameters and fin aspect ratio of sub-20nm SOI-FinFET: an analysis towards analog and RF circuit design;Mohapatra;IEEE Trans. Nanotechnol.,2015
4. Characterization and optimization of inverted-T FinFET under nanoscale dimensions;Yu;IEEE Trans. Electron. Dev.,2018
5. Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance;Skotnicki,2005