Investigation on electrical parameters in nanowire FET and nanosheet FET including trap charges and its circuit applications

Author:

Gogoi Manosh Protim,Saha RajeshORCID,Baishya Srimanta

Funder

CSIR

Publisher

Elsevier BV

Reference39 articles.

1. Nanosheet field effect transistors-A next generation device to keep Moore's law alive: an intensive study;Ajayan;Microelectron. J.,2021

2. Nanowire transistors without junctions;Colinge;Nature Nanotechnol,2010

3. Effects of spacer and singlecharge trap on voltage transfer characteristics of gate-all-around silicon nanowire CMOS devices and circuits;Kola;Proc. IEEE 20th Int. Conf. Nanotechnol. (IEEE-NANO),2020

4. Self-heating and interface traps assisted early aging revelation and reliability analysis of negative capacitance FinFET;Jaisawal;Proc. 7th IEEE Electron Devices Technol. Manuf. Conf. (EDTM),2023

5. Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET;Das;IEEE Trans. Electron Devices,2020

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