Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks-Reference-Cited by-同舟云学术

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Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks

Published:2024-12 Issue: Volume:609 Page:128480
ISSN:0925-2312
Container-title:Neurocomputing
language:en
Short-container-title:Neurocomputing

Author:

Liu Junxiu,Jiang Dong,Fu Qiang^ORCID,Luo Yuling,Deng Yaohua,Qin Sheng,Zhang Shunsheng

Publisher

Elsevier BV

Reference35 articles.

1. Towards artificial general intelligence with hybrid Tianjic chip architecture;Pei;Nature,2019

2. Low cost interconnected architecture for the hardware spiking neural networks;Luo;Front. Neurosci.,2018

3. Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations;Carrillo;IEEE Trans. Parallel Distrib. Syst.,2013

4. Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers;Carrillo;Neural Netw.,2012

5. An efficient, low-cost routing architecture for spiking neural network hardware implementations;Luo;Neural Process. Lett.,2018

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