SMA: A constructive partitioning based mapping approach for Networks-on-Chip

Author:

Alagarsamy Aravindhan,Mahilmaran Sundarakannan,Gopalakrishnan Lakshminarayanan,Ko Seok-Bum

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference21 articles.

1. A survey of research and practices of network-on-chip;Bjerregaard;ACM Comput. Surv.,2006

2. S. Tosun, O. Ozturk, M. Ozen, An ILP formulation for application mapping onto network-on-chips, in: Proc. on Int. Conf. Appl. Inf. Commun. Technol, ICAICT, 2009, pp. 1–5.

3. S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, A network on chip architecture and design methodology, in: Proc. on ISVLSI, 2002, pp. 117–124.

4. Extending kernighan-lin partitioning heuristic for application mapping onto networks-on-chip;Sahu;J. Syst. Archit.,2014

5. M. Jiayi, Z. Wencan, Y. Takeshi, Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip, in: Proc. on ISOCC, 2016, pp. 83–84.

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