Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference36 articles.
1. Why systolic architectures?;Kung;Computer,1982
2. N.P. Jouppi, et al., In-Datacenter Performance Analysis of a Tensor Processing Unit, in: Intern. Symp. on Comp. Arch. (ISCA), 2017, pp. 1–12.
3. A. Samajdar, et al., A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim, in: IEEE Intern. Symp. on Perf. Analysis of Systems and Software (ISPASS), 2020.
4. X. Wei, et al., Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs, in: Design Automation Conference (DAC), 2017.
5. B. Asgari, R. Hadidi, H. Kim, Meissa: Multiplying matrices efficiently in a scalable systolic architecture, in: IEEE Intern. Conf. on Computer Design (ICCD), 2020, pp. 130–137.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献