Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP-Reference-Cited by-同舟云学术

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Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP

Published:2024-03-25 Issue: Volume:194 Page:1-6
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Container-title:2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Author:

Henkes Tim¹,Reith Steffen¹,Stöttinger Marc¹,Herfurth Norbert²,Panic Goran²,Wälde Julian³,Buschkowski Fabian⁴,Sasdrich Pascal⁴,Lüth Christoph⁵,Funck Milan⁵,Kiyan Tuba⁶,Weber Arnd⁷,Boeck Detlef⁸,Rathfelder René⁹,Grawunder Torsten¹⁰

Affiliation:

1. RheinMain University of Applied Sciences,FB Design Computer Science Media,Wiesbaden,Germany

2. IHP - Leibniz-Institut für innovative Mikroelektronik,Frankfurt (Oder),Germany

3. ACE, Fraunhofer SIT,Darmstadt,Germany

4. Ruhr-University Bochum,Chair for Security Engineering,Bochum,Germany

5. Deutsches Forschungszentrum für Künstliche Intelligenz,Bremen,Germany

6. Technische Universitaet Berlin,Security in Telecommunications,Berlin,Germany

7. Bollschweil,Germany

8. Elektrobit Automotive GmbH,Erlangen,Germany

9. Software Powertrain, IAV GmbH,Berlin,Germany

10. Swissbit Germany AG,Berlin,Germany

Funder

BMBF

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10546498/10546499/10546500.pdf?arnumber=10546500

Reference14 articles.

1. Titan: enabling a transparent silicon root of trust for cloud;Johnson,2018

2. Caliptra: A datacenter system on a chip (soc) root of trust (rot);Kelly;Open Compute Project, Tech. Rep.,2022

3. Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification

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