The Investigation of graded channel effect on Analog/Linearity Parameter Analysis of junctionless surrounded gate graded channel MOSFET

Abstract

Abstract Linarity analysis of nanoscaled devices is a vital issue as nonlinearity behaviour is exhibited by them when employed in circuits for microwave and RF applications. In this work a junctionless surrounded gate graded channel MOSFET (JLSGGC MOSFET) is investigated thoroughly to analyse its linearity performance with the help of ATLAS tool of technology computer aided design (TCAD). The proposed device is compared systematically with the conventional junstionless surrounded gate MOSFET(JLSG MOSFET) to investigate their linearity. To evaluate the linearity, the figure of merits (FOMs) such as higher order tranconductances (Gm1 ,Gm2), intercept points(VIP2, VIP3, IIP3), IMD3 and 1 dB– compression point(P1 dB) are considered. The linearity of our proposed device improves by 35.5% in the view of the compression point in comparison to JLSG MOSFET before threshold voltage region of operation. The simulation results reveal a substantial enhancement in the linearity performance of the JLSGGC MOSFET. Improved linearity behaviour of JLSGGC MOSFET make it suitable for wireless RF and system on chip applications.