Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction
Author:
Affiliation:
1. GLOBALFOUNDRIES Inc. USMaltaNew York12020USA
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2019.3954
Reference9 articles.
1. Performance optimization study of FinFETs considering parasitic capacitance and resistance;An T.;JSTS: J. Semicond. Technol. Sci.,2014
2. Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random‐access memory cells;Huang B.R.;Jpn. J. Appl. Phys.,2017
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