1. Kim, B., T. Matthias, M. Wimplinger, P. Kettner, and P. Lindner, “Comparison of Enabling Wafer Bonding Techniques for TSV Integration”, ASME Paper No. IMECE2010-400002.
2. Chen, K., S. Lee, P. Andry, C. Tsang, A. Topop, Y. Lin, Y., J. Lu, A. Young, M., Ieong, and W. Haensch, W., “Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits”, IEEE Proceedings of International Electron Devices Meeting, (IEDM 2006), San Francisco, CA, December 11–13, 2006, pp. 367-370.
3. Liu, F., Yu, R., Young, A., Doyle, J., Wang, X., Shi, L., Chen, K., Li, X., Dipaola, D., Brown, D., Ryan, C., Hagan, J., Wong, K., Lu, M., Gu, X., Klymko, N., Perfecto, E., Merryman, A., Kelly K., Purushothaman, S., Koester, S., Wisnieff, R., and Haensch, W., “A 300- Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hyprid Cu-Adhesive Bonding”, IEEE Proceedings of IEDM, December 2008, pp. 1–4.
4. Yu, R., Liu, F., Polastre, R., Chen, K., Liu, X., Shi, L., Perfecto, E., Klymko, N., Chace, M., Shaw, T., Dimilia, D., Kinser, E., Young, A., Purushothaman, S., Koester, S., and Haensch W., “Reliability of a 300-mm-compatible 3DI Technology Base on Hybrid Cu-adhesive Wafer Bonding”, Proceedings of Symposium on VLSI Technology Digest of Technical Papers, 2009, pp. 170–171.
5. Shigetou, A. Itoh, T., Sawada, K., and Suga, T., “Bumpless Interconnect of 6-um pitch Cu Electrodes at Room Temperature”, In IEEE Proceedings of ECTC, Lake Buena Vista, FL, May 27–30, 2008, pp. 1405-1409.