Optimization of Device Dimensions of High-k Gate Dielectric Based DG-TFET for Improved Analog/RF Performance
Author:
Funder
NPIU
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01127-y.pdf
Reference29 articles.
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3. Wu EY, Nowak EJ, Vayshenker A, Lai WL, Harmon DL (2002) CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics. IBM Journal of Research and Development 46:287–298. doi: 10.1147/rd.462.0287. https://doi.org/10.1007/s11664-021-08811-0
4. Goyal V, Tayal S, Meena S, Gupta R (2021) Impact of interfacial layer thickness on gate-stack-based DGTFET: an analog/RF prospective. IOP Conference Series: Materials Science and Engineering 1070:012081. https://doi.org/10.1088/1757-899X/1070/1/012081
5. Bhol K, Nanda U (2021) Nanowire array-based MOSFET for future CMOS technologyto attain the ultimate scaling limit. Silicon 1-9. https://doi.org/10.1007/s12633-020-00909-0
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