A Novel Nanoscale SOI MOSFET by Using a P-N Junction and an Electrically Hole Free Region to Improve the Electrical Characteristics
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01304-z.pdf
Reference29 articles.
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3. Zareiee M, Mehrad M (2017) A reliable nano device with appropriate performance in high temperatures. ECS J Solid State Sci Technol 6(4):M50
4. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliab 4(1):99–109
5. Fukuda Y, Ito S, Ito M (2001) SOI-CMOS device technology. OKI Tech Rev 4:54
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1. A nanoscale junctionless FET to amend the electric field distribution using a β-Ga2O3 packet;Journal of Materials Science: Materials in Electronics;2023-08
2. High performance nanoscale SOI MOSFET with enhanced gate control;Micro and Nanostructures;2023-03
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