VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution)-Reference-Cited by-同舟云学术

VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution)

Published:2020 Issue: Volume: Page:383-387
ISSN:0302-9743
Container-title:Tools and Algorithms for the Construction and Analysis of Systems
language:
Short-container-title:

Author:

Afzal Mohammad,Chakraborty Supratik^ORCID,Chauhan Avriti,Chimdyalwar Bharti,Darke Priyanka,Gupta Ashutosh,Kumar Shrawan,Babu M Charles,Unadkat Divyesh^ORCID,Venkatesh R

Abstract

AbstractVeriAbs is a strategy selection based reachability verifier for C code. It analyzes the structure of loops, and intervals of inputs to choose one of the four verification strategies implemented in VeriAbs. In this paper, we present VeriAbs version 1.4 with updates in three strategies. We add an array verification technique called full-program induction, and enhance the existing techniques of loop pruning, k-path interval analysis, and disjunctive loop summarization. These changes have improved the verification of programs with arrays, and unstructured loops and unstructured control flows.

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-45237-7_25

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